Many existing computer systems or computing devices include different types of memory, for example, dynamic random-access memory (DRAM) and flash memory, which have different communication formats and/or different signaling rates. Because of size and cost constraints in these systems, it is often useful to communicate with these different types of memory using a minimum number of interface pins.
Some existing systems address this design constraint by including a traditional double-data-rate-style interface to flash memory. In these systems, the flash memory is operated as an independent rank on multi-drop command/address (CA) and data (DQ) links. Unfortunately, on multi-drop links, a double-date-rate-style interface can degrade the signal-integrity and, thus, the communication performance, of these links. This degradation in communication performance can exacerbate problems that arise as a consequence of differences in the signaling rates of the different types of memory.
Hence, there is a need for a device that supports communication with different types of memory without the above-described problems.
Note that like reference numerals refer to corresponding parts throughout the drawings.